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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781 analog devices, inc. all rights reserved. ad818 low cost, low power video op amp features low cost excellent video performance 55 mhz 0.1 db bandwidth (gain = +2) 0.01% and 0.05 differential gain and phase errors high speed 130 mhz bandwidth (3 db, g = +2) 100 mhz bandwidth (3 db, g+ = ?) 500 v/ s slew rate 80 ns settling time to 0.01% (v o = 10 v step) high output drive capability 50 ma minimum output current ideal for driving back terminated cables flexible power supply specified for single (+5 v) and dual ( 5 v to 15 v) power supplies low power: 7.5 ma max supply current available in 8-lead soic and 8-lead pdip connection diagram 8-lead plastic mini-dip (n) and soic (r) packages null ?n +in output null 1 2 3 4 8 7 6 5 ? s top view +v s ad818 nc nc = no connect general description the ad818 is a low cost video op amp optimized for use in video applications that require gains equal to or greater than +2 or ?. the ad818? low differential gain and phase errors, single supply functionality, low power, and high output drive make it ideal for cable driving applications such as video cameras and professional video equipment. with video specs like 0.1 db flatness to 55 mhz and low differ- ential gain and phase errors of 0.01% and 0.05 , along with 50 ma of output current, the ad818 is an excellent choice for any video application. the 130 mhz 3 db bandwidth (g = +2) and 500 v/ m s slew rate make the ad818 useful in many high speed applications including video moni tors, catv, color copiers, image scanners, and fax machines. the ad818 is fully specified for operation with a single +5 v power supply and with dual supplies from 5 v to 15 v. this power supply flexibility, coupled with a very low supply current of 7.5 ma and excellent ac characteristics under all power sup- ply conditions, make the ad818 the ideal choice for many demanding yet power sensitive applications. the ad818 is a voltage feedback op amp and excels as a gain stage in high speed and video systems (gain 2, or gain ?). it achieves a settling time of 45 ns to 0.1%, with a low input offset voltage of 2 mv max. the ad818 is available in low cost, small 8-lead pdip and soic packages. ad818 1k +15v r bt 75 r t 75 v in 75 ?5v 0.1f 2.2f 0.01f 2.2f 1k figure 1. video line driver 0.03 15 0.06 0.04 0.05 510 differential phase (degrees) supply voltage (v) differential gain (%) 0.02 0.01 0.00 diff gain diff phase figure 2. differential gain and phase vs. supply d 2010 .461-3113
rev. ? ad818?pecifications (@ t a = 25 c, unless otherwise noted.) ad818a parameter conditions v s min typ max unit dynamic performance ? db bandwidth gain = +2 5 v 70 95 mhz 15 v 100 130 mhz 0 v, +5 v 40 55 mhz gain = ? 5 v 50 70 mhz 15 v 70 100 mhz 0 v, +5 v 30 50 mhz bandwidth for 0.1 db flatness gain = +2 5 v 20 43 mhz c c = 2 pf 15 v 40 55 mhz 0 v, +5 v 10 18 mhz gain = ? 5 v 18 34 mhz c c = 2 pf 15 v 40 72 mhz 0 v, +5 v 10 19 mhz full power bandwidth * v out = 5 v p-p r load = 500 w 5 v 25.5 mhz v out = 20 v p-p r load = 1 k w 15 v 8.0 mhz slew rate r load = 1 k w 5 v 350 400 v/ m s gain = ? 15 v 450 500 v/ m s 0 v, +5 v 250 300 v/ m s settling time to 0.1% ?.5 v to +2.5 v 5 v 45 ns 0 v?0 v step, a v = ? 15 v 45 ns settling time to 0.01% ?.5 v to +2.5 v 5 v 80 ns 0 v?0 v step, a v = ? 15 v 80 ns total harmonic distortion f c = 1 mhz 15 v 63 db differential gain error ntsc 15 v 0.005 0.01 % (r l = 150 w )g ain = +2 5 v 0.01 0.02 % 0 v, +5 v 0.08 % differential phase error ntsc 15 v 0.045 0.09 degrees (r l = 150 w )g ain = +2 5 v 0.06 0.09 degrees 0 v, +5 v 0.1 degrees cap load drive 10 pf input offset voltage 5 v to 15 v 0.5 2 mv t min to t max 3mv offset drift 10 m v/ c input bias current 5 v, 15 v 3.3 6.6 m a t min 10 m a t max 4.4 m a input offset current 5 v, 15 v 25 300 na t min to t max 500 na offset current drift 0.3 na/ c open-loop gain v out = 2.5 v 5 v r load = 500 w 35 v/mv t min to t max 2 v/mv r load = 150 w 24 v/mv v out = 10 v 15 v r load = 1 k w 69 v/mv t min to t max 3 v/mv v out = 7.5 v 15 v r load = 150 w (50 ma output) 3 5 v/mv common-mode rejection v cm = 2.5 v 5 v 82 100 db v cm = 12 v 15 v 86 120 db t min to t max 15 v 84 100 db d
rev. ad818 ? ad818a parameter conditions v s min typ max unit power supply rejection v s = 5 v to 15 v 80 90 db t min to t max 80 db input voltage noise f = 10 khz 5 v, 15 v 10 nv/ hz input current noise f = 10 khz 5 v, 15 v 1.5 pa/ hz input common-mode voltage range 5 v +3.8 +4.3 v ?.7 ?.4 v 15 v +13 +14.3 v ?2 ?3.4 v 0 v, +5 v +3.8 +4.3 v +1.2 +0.9 v output voltage swing r load = 500 w 5 v 3.3 3.8 v r load = 150 w 5 v 3.2 3.6 v r load = 1 k w 15 v 13.3 13.7 v r load = 500 w 15 v 12.8 13.4 v r load = 500 w 0 v, +5 v 1.5, 3.5 v output current 15 v 50 ma 5 v 50 ma 0 v, +5 v 30 ma short-circuit current 15 v 90 ma input resistance 300 k w input capacitance 1.5 pf output resistance open loop 8 w power supply operating range dual supply 2.5 18 v single supply +5 +36 v quiescent current 5 v 7.0 7.5 ma t min to t max 5 v 7.5 ma 15 v 7.5 ma t min to t max 15 v 7.0 7.5 ma * full power bandwidth = slew rate/(2 p v peak ). specifications subject to change without notice. d
rev. ? ad818 absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic (n) . . . . . . . . . . . . . . . . . . . . . . see derating curves small outline (r) . . . . . . . . . . . . . . . . . see derating curves input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 v output short-circuit duration . . . . . . . . see derating curves storage temperature range (n, r) . . . . . . . . ?5 c to +125 c operating temperature range . . . . . . . . . . . . ?0 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead plastic package, ja = 90 c/w; 8-lead soic package, ja = 155 c/w. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad818 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 2.0 0 ?0 90 1.5 0.5 ?0 1.0 50 70 30 10 ?0 80 ?0 40 60 200 ?0 ambient temperature (c) maximum power dissipation (w) 8-lead mini-dip package 8-lead soic package t j = 150 c figure 3. maximum power dissipation vs. temperature for different package types metallization photograph dimensions shown in inches and (mm) ?nput 2 +input 3 6 output 4 ? s +v s 7 offset null 8 offset null 1 0.0559 (1.42) 0.0523 (1.33) d
rev. t ypical performance characteristics?d818 ? 20 0 020 15 5 5 10 10 15 input common-mode range ( v) supply voltage (v) ? cm +v cm tpc 1. common-mode voltage range vs. supply load resistance () 30 0 10 10k output voltage swing (v p-p) 5 1k 100 10 15 20 25 v s = 15v v s = 5v tpc 2. output voltage swing vs. load resistance 600 200 020 500 300 5 400 10 15 slew rate (v/s) supply voltage (v) tpc 3. slew rate vs. supply voltage 20 0 020 15 5 5 10 10 15 supply voltage (v) output voltage swing ( v) r l = 150 r l = 500 tpc 4. output voltage swing vs. supply ?0c 8.0 6.0 02 0 7.5 6.5 5 7.0 10 15 supply voltage (v) quiescent supply current (ma) +25c +85c tpc 5. quiescent supply current vs. supply voltage 100 1 0.01 1k 10k 100m 10m 1m 100k 0.1 10 frequency (hz) closed-loop output impedance () tpc 6. closed-loop output impedance vs. frequency d
rev. ? ad818 7 1 140 4 2 ?0 3 ?0 6 5 120 806040 100 200?0 temperature (c) input bias current (a) tpc 7. input bias current vs. temperature 70 30 ?0 140 60 40 ?0 50 100 120 806040200?0 95 85 75 65 55 phase margin (degrees) ?db bandwidth (mhz) temperature (c) phase margin gain/bandwidth tpc 8. ? db bandwidth and phase margin vs. temperature, gain = +2 9 6 3 100 1k 10k 4 5 7 8 load resistance () open-loop gain (v/mv) 5v 15v tpc 9. open-loop gain vs. load resistance 130 30 140 90 50 ?0 70 ?0 110 120100806040200?0 temperature (c) short circuit current (ma) sink current source current tpc 10. short-circuit current vs. temperature 100 ?0 1g 40 0 10k 20 1k 80 60 100m 10m 1m 100k frequency (hz) 100 40 0 20 80 60 phase margin (degrees) open-loop gain (db) phase 5v or 15v supplies 15v supplies r l = 1k 5v supplies r l = 1k tpc 11. open-loop gain and phase margin vs. frequency 100 10 100m 30 20 1k 100 40 50 60 70 80 90 10m 1m 100k 10k frequency (hz) psr (db) +supply ?upply tpc 12. power supply rejection vs. frequency d
rev. ad818 ? 120 40 1k 10m 100 60 10k 80 100k 1m frequency (hz) cmr (db) tpc 13. common-mode rejection vs. frequency 10 ?0 160 ? ? 20 ? 0 2 ? 0 4 6 8 140 120 100 806040 settling time (ns) output swing from 0 to v (v) 0.01% 0.1% 1% 1% 0.01% 0.1% tpc 14. output swing and error vs. settling time 50 0 10m 30 10 10 20 1 40 1m 100k 10k 1k 100 frequency (hz) input voltage noise (nv/ hz) tpc 15. input voltage noise spectral density vs. frequency 30 10 0 100k 1m 100m 10m 20 output voltage (v p-p) frequency (hz) r l = 1k r l = 150 tpc 16. output voltage vs. frequency ?0 ?00 10m ?0 ?0 1k ?0 100 ?0 ?0 1m 100k 10k frequency (hz) harmonic distortion (db) second harmonic r l = 150 2v p-p third harmonic tpc 17. harmonic distortion vs. frequency 650 250 ?0 140 550 350 ?0 450 100 120 806040200?0 temperature (c) slew rate (v/s) tpc 18. slew rate vs. temperature d
rev. ? ad818 0.03 15 0.06 0.04 0.05 510 differential phase (degrees) supply voltage (v) differential gain (%) 0.02 0.01 0.00 diff gain diff phase tpc 19. differential gain and phase vs. supply voltage 6 1 5 4 3 2 7 8 9 10 gain (db) frequency (hz) 15v 0.1db v s c c flatness 15v 2pf 55mhz 5v 1pf 43mhz +5v 1pf 18mhz 1m 10m 100m 1g 5v +5v 1k 150 v out ad818 c c 1k v in tpc 20. closed-loop gain vs. frequency (g = +2) 10 0 ?0 ? ? ? ? 2 4 6 8 gain (db) frequency (hz) 15v 0.1db v s flatness 15v 72mhz 5v 34mhz +5v 19mhz 1m 10m 100m 1g 5v +5v 1k 150 v out ad818 2pf 1k v in tpc 21. closed-loop gain vs. frequency (g = ?) ad818 r l v out hp pulse (ls) or function (ss) generator 1k 50 v in tektronix 7a24 preamp 1k c f +v s 3.3f 0.01f 0.01f 3.3f ? s tektronix p6201 fet probe tpc 22. inverting amplifier connection 10 90 100 0% 2v 50ns 2v tpc 23. inverter large signal pulse response; v s = 5 v, c f = 1 pf, r l = 1 k w 10 90 100 0% 200mv 10ns 200mv tpc 24. inverter small signal pulse response; v s = 5 v, c f = 1 pf, r l = 150 w d
rev. ad818 ? 10 90 100 0% 5v 50ns 5v tpc 25. inverter large signal pulse response; v s = 15 v, c f = 1 pf, r l = 1 k w 10 90 100 0% 200mv 10ns 200mv tpc 26. inverter small signal pulse response; v s = 15 v, c f = 1 pf, r l = 150 w 10 90 100 0% 200mv 10ns 200mv tpc 27. inverter small signal pulse response; v s = 5 v, c f = 0 pf, r l = 150 w ad818 r l v out hp pulse (ls) or function (ss) generator 100 50 v in tektronix 7a24 preamp 1k c f +v s 3.3f 0.01f 0.01f 3.3f ? s tektronix p6201 fet probe 1k tpc 28. noninverting amplifier connection 10 90 100 0% 1v 50ns 2v tpc 29. noninverting large signal pulse response; v s = 5 v, c f = 1 pf, r l = 1 k w 10 90 100 0% 100mv 10ns 200mv tpc 30. noninverting small signal pulse response; v s = 5 v, c f = 1 pf, r l = 150 w d
rev. ?0 ad818 10 90 100 0% 5v 50ns 5v tpc 31. noninverting large signal pulse response; v s = 15 v, c f = 1 pf, r l = 1 k w 10 90 100 0% 100mv 10ns 200mv tpc 32. noninverting small signal pulse response; v s = 15 v, c f = 1 pf, r l = 150 w 10 90 100 0% 100mv 10ns 200mv tpc 33. noninverting small signal pulse response; v s = 5 v, c f = 0 pf, r l = 150 w d
rev. ad818 ?1 ?n +in null 1 null 8 output +v s ? s figure 4. ad818 simplified schematic theory of operation the ad818 is a low cost video operational amplifier designed to excel in high performance, high output current video applications. the ad818 (figure 4) consists of a degenerated npn differen- tial pair driving matched pnps in a folded-cascode gain stage. the output buffer stage employs emitter followers in a class ab amplifier that delivers the necessary current to the load, while maintaining low levels of distortion. the ad818 will drive terminated cables and capacitive loads of 10 pf or less. as the closed-loop gain is increased, the ad818 will drive heavier capacitive loads without oscillating. input considerations an input protection resistor (r in in tpc 28) is required in circuits where the input to the ad818 will be subjected to tran- sients of continuous overload voltages exceeding the 6 v maximum differential limit. this resistor provides protection for the input transistors by limiting their maximum base current. for high performance circuits, it is recommended that a ?al- ancing?resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. the balancing resistor equals the parallel combination of r in and r f and thus provides a matched impedance at each input terminal. the offset voltage error will then be reduced by more than an order of magnitude. grounding and bypassing when designing high frequency circuits, some special precautions are in order. circuits must be built with short interconnect leads. when wiring components, care should be taken to provide a low resistance, low inductance path to ground. sockets should be avoided, since their increased interlead capacitance can degrade circuit bandwidth. feedback resistors should be of low enough value ( 1 kw ) to ensure that the time constant formed with the inherent stray capacitance at the amplifier? summing junction will not limit performance. this parasitic capacitance, along with the parallel resistance of r f r in , forms a pole in the loop transmission, which may result in peaking. a small capacitance (1 pf? pf) may be used in parallel with the feedback resistor to neutralize this effect. power supply leads should be bypassed to ground as close as possible to the amplifier pins. ceramic disc capacitors of 0.1 m f are recommended. 10k ? s v os adjust +v s ad818 figure 5. offset null configuration offset nulling the input offset voltage of the ad818 is inherently very low. however, if additional nulling is required, the circuit shown in figure 5 can be used. the null range of the ad818 in this configuration is 10 mv. single supply operation another exciting feature of the ad818 is its ability to perform well in a single supply configuration. the ad818 is ideally suited for applications that require low power dissipation and high output current. referring to figure 6, careful consideration should be given to the proper selection of component values. the choices for this particular circuit are: r1 + r3 r2 combine with c1 to form a low frequency corner of approximately 10 khz. c4 was inserted in series with r4 to maintain amplifier stability at high frequency. combining r3 with c2 forms a low-pass filter with a corner frequency of approximately 500 hz. this is needed to maintain amplifier psrr, since the supply is connected to v in through the input divider. the values for r2 and c2 were chosen to demonstrate the ad818? exceptional output drive capability. in this configuration, the output is centered around 2.5 v. in order to eliminate the static dc current associ ated with this level, c3 was inserted in series with r l . r2 3.3k r1 3.3k r3 100 c2 3.3f v in c1 0.01f c4 0.001f r4 1k ad818 v out v s 3.3f 0.01f select c1, r1, r2 for desired low frequency corner. c3 0.1f r l 150 1k figure 6. single-supply amplifier configuration d
rev. ?2 ad818 ad818 settling time settling time primarily comprises two regions. the first is the slew time in which the amplifier is overdriven, where the output voltage rate of change is at its maximum. the second is the linear time period required for the amplifier to settle to within a specified percentage of the final value. measuring the rapid settling time of the ad818 (45 ns to 0.1% and 80 ns to 0.01%?0 v step) requires applying an input pulse with a very fast edge and an extremely flat top. with the ad818 configured in a gain of ?, a clamped false summing junction responds when the output error is within the sum of two diode voltages (approximately 1 v). the signal is then amplified 20 times by a clamped amplifier whose output is connected directly to a sampling oscilloscope. ad829 100 0.47f 0.01f ? s 0.47f 0.01f +v s short, direct connection to tektronix type 11402 oscilloscope preamp input section 15pf 1m 2 hp2835 error amplifier v error output 10 1.9k 100 ad818 0.01f ? s 0.01f 2.2f +v s 2.2f 10pf scope probe capacitance tektronix p6201 fet probe to tektronix type 11402 oscilloscope preamp input section 500 5pf?8pf device under test note use circuit board with ground plane false summing node null adjust 1k 100 1k 50 coax cable ttl level signal generator 50hz output 1, 14 7, 8 digital ground analog ground 0 to 10v power supply ei&s dl1a05gm mercury relay error signal output 500 50 2 hp2835 figure 7. settling time test circuit a high performance video line driver the buffer circuit shown in figure 8 will drive a back-termi nated 75 w video line to standard video levels (1 v p-p) with 0.1 db gain flatness to 55 mhz with only 0.05 and 0.01% differential phase and gain at the 3.58 mhz ntsc subcarrier frequency. this level of performance, which meets the requirements for high definition video displays and test equipment, is achieved using only 7 ma quiescent current. 1k 1k r t 75 75 +15v r bt 75 v in r t 75 ?5v 2.2f 0.01f ad818 0.01f 2.2f figure 8. video line driver d
rev. ad818 ?3 a high speed, 3-op amp in amp the circuit of figure 11 uses three high speed op amps: two ad818s and an ad817. this high speed circuit lends itself well to ccd imaging and other video speed applications. it has the optional flexibility of both dc and ac trims for common-mode rejection, plus the ability to adjust for minimum settling time. +v in r g 2pf 5pf a1 ad818 ? in v out 2pf?pf settling time ac cmr adjust r l 2k 970 50 dc cmr adjust 3pf +15v common ?5v 10f 10f +v s ? s 0.1f 0.1f 1f 1f pin 7 each amplifier 0.1f 0.1f pin 4 each amplifier each amplifier bandwidth, settling time, and total harmonic distortion vs. gain gain r g cadj (pf) small signal bandwidth settling time to 0.1% thd + noise below input level @ 10khz 3 10 100 1k 222 20 2? 2? 2? 14.7mhz 4.5mhz 960khz 200ns 370ns 2.5s 82db 81db 71db 1k 5pf 1k 1k 1k 1k a2 ad818 a3 ad818 figure 11. high speed 3-op amp in amp differential line receiver the differential receiver circuit of figure 9 is useful for many applications?rom audio to video. it allows extraction of a low level signal in the presence of common-mode noise, as shown in figure 10. v out 2pf differential input +5v ?v output ad818 0.01f 2.2f 0.01f 2.2f 2pf 1k 1k 1k 1k v b v a figure 9. differential line receiver 10 90 100 0% 1v 2v 20ns output v a figure 10. performance of line receiver, r l = 150 w , g = +2 d
ad818 C14C rev. d outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 12. 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in m illimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 13. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
ad818 rev. d C15C ordering guide model 1 temperature range package description package option ad818an ?40c to +85c 8-lead plastic pdip n-8 ad818anz ?40c to +85c 8-lead plastic pdip n-8 ad818ar ?40c to +85c 8-lead soic_n r-8 AD818ARZ ?40c to +85c 8-lead soic_n r-8 ad818ar-reel ?40c to +85c 8-lead soic_n, 13 tape and reel r-8 AD818ARZ-reel ?40c to +85c 8-lead soic_n, 13 tape and reel r-8 ad818ar-reel7 ?40c to +85c 8-lead soic_n, 7 tape and reel r-8 AD818ARZ-reel7 ?40c to +85c 8-lead soic_n, 7 tape and reel r-8 ad818ar-ebz ?40c to +85c evaluati on board for 8-lead soic_n 1 z = rohs compliant part. revision history 10/10rev. c to rev. d updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 5/03rev. b to rev. c renumbered figures and tpcs ........................................ universal changes to specifications ................................................................ 2 changes to ordering guide ............................................................ 4 changes to figures 9 and 10 ......................................................... 12 updated outline dimensions ....................................................... 14 ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00872-0-10/10(d)

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